MISFET (metal-insulator-semiconductor field-effect transistor), or IGFET (isolated-gate field-effect transistor) devices as they are sometimes called, have been known for some time now and play an important role in modern integrated metal-oxide-semiconductor FET known in the art as the MOSFET.
The MOSFET is typically fabricated using a four-mask process wherein the heavily doped source and drain regions of one type of impurity are diffused into a substrate doped with the other type of impurity. An oxide grown over the surface of the substrate separating the source and drain regions insulates a metallic gate electrode from the semiconductive materials.
Due to the area of opposite conductivity type semiconductor separating the source and drain regions, a pair of back-to-back junction diodes are formed between the source and drain contacts, and as a result, the channel current between source and drain is essentially zero for zero-gate bias. However, by applying voltage to the gate electrode, the polarity of which is determined by the conductivity-type of the channel region, a depletion region is formed at the surface of the semiconductor between source and drain which, with increased voltage, causes an inversion to occur, thus providing a conductive channel therebetween of the same conductivity as the source and drain regions. When this occurs, ohmic conduction begins between source and drain, the current flow being determinable by the magnitude of the voltage applied to the gate.
Although MISFET's fabricated in accordance with this and other prior art techniques have been used extensively in the past, these methods and the resulting devices typically suffer several disadvantages. One disadvantage of prior art methods is the lack of flexibility in terms of making N or P-channel devices from the same process using the same set of masks, or in fabricating simultaneously, both N and P-channel devices on the same substrate. Some N-channel processing methods even produce unstable and/or unpredictable device characteristics. Using some prior art methods, large shifts in device thresholds may occur during assembly or under bias and stress conditions applied to the device after assembly.
In addition, some prior art techniques result in low and unstable field inversion thresholds. Others fall to provide adequate protection against destruction of the gate dielectric through static electricity. Furthermore, many of these techniques do not provide topside contact to the substrates, thus space-consuming metal interconnects are necessary and certain packaging and hybridizing restraints result.